Ferramenta para análise e monitoramento de erros em memórias protegidas por ECC

Abstract

Due to the shrinkage of the integrated devices, memories have a high probability of presenting multiple bit upset, corrupting the stored data, representing a real concern for critical applications, in which data reliability is a necessity. Therefore, some techniques are known and implemented in order to mitigate this real problem, among the best known and implemented are error-correcting codes. These codes implement algorithms that increase memory reliability through techniques that allow the identification and sometimes the correction of faults in memory cells. Among the reasons that make this technique so used are the low complexity of its implementation. However, assessing the effectiveness of these codes at the hardware level can be a difficult assignment. Therefore, I propose the creation of a tool that seeks to facilitate the analysis of these codes by monitoring the execution of some Error-Correcting Codes in Memory. The tool helps to evaluate the performance of these codes in memory in a clear and objective way, using graphs and comparison data. For that, some codes (Hamming, CLC, extended CLC and MRSC) are implemented in the microcontroller device TMS570LS0432. Among the graphics provided by the tool is the correction curve that can be compared with the number of errors injected. It also presents a comparative of efficiency between corrections made in each code. Being a useful tool for the analysis, or even study, of protection techniques used in devices, mainly the so-called fault tolerant.