Um gerador de arquiteturas SoC para execução de redes neurais convolucionais em FPGAs

Abstract

Convolutional Neural Networks (CNNs) are widely used in several applications. Currently, there is an interest in the development and execution of these networks in embedded systems. To facilitate this development for applications in embedded systems, this work presents an automatic system for the generation of System on Chip architectures for the execution of CNNs in Field Programmable Gate Arrays (FPGAs). It was used in the implementation of a Co-Design technique to generate a System on Chip structure, resulting in a system composed of software and hardware subsystems. In the hardware subsystem development uses a High Level Synthesis (HLS) technique to generate a coprocessor in the form of Intellectual Property (IP) specific to the convolution layer. This is a layer responsible for about 63 % of the total running time of CNN software used as a test case. The results presented that, in the generated architecture, the convolution was executed 15.2 times faster than the convolution implemented in software.