Proteção otimizada de buffers de redes intrachip através de códigos de correção de erros

Abstract

Newest technologies of integrated circuits manufacture allow billions of transistors arranged in a single chip, which requires a communication architecture with high scalability and parallelism degree, such as a Network-on-Chip (NoC). As the technology scales down, the probability of Multiple Cell Upsets (MCUs) increases, being Error Correction Code (ECC) the one of the most used techniques to protect stored information against MCUs. NoC buffers are components that suffer from MCUs induced by diverse sources, such as radiation and electromagnetic interference. Thereby, applying ECCs in NoC buffers may come as a solution for reliability issues, although increasing the design cost and requiring a buffer with higher storage capacity. Solutions as Triple Modular Redundancy (TMR) that replicates three times the component that must be protected, and electromagnetic shielding that applies a conductive material to protect a component, have a high cost and may be impracticable for design. This work proposes a new model of protection implementation for buffers that applies four ECCs to deal with MCUs and enhance the protected information storage, pursuing to reduce the area and power required for ECC implementation. We guide the optimized buffer evaluation by measuring the buffer area, power overhead, fault tolerance efficiency and performance of the proposed technique. All tests included the comparison with a non-optimal appliance of ECC in a NoC buffer. The results show the proposed technique reduces the area and power overhead in buffers with ECC and increase the reliability against MCUs in 3%, however, it causes a small performance decrease.