Redução de latência em redes intrachip tolerantes a falha através do uso de múltiplos caminhos

Abstract

Digital circuit technologies are reaching nanometer scales and thereby increasing the likelihood of permanent, transient, and intermittent failures. As a result, the demand for fault tolerance strategies is the main subject of many types of research targeting Systems-on-Chip designs. In particular, retransmission mechanisms are one of the most used solutions in Networks-on-Chip. However, these mechanisms introduce an extra delays in packet latency. This work proposes the use of multiple paths (i.e minimum or not) as a way to reduce the extra delay caused by the impact of retransmissions in critical systems (i.e where latency is a critical problem). The technique encompasses using different sets of paths to create the routing tables. Two metrics are proposed to classify the different paths for a communication pair considering the probability of failure of the communication links and the amount of new communication links added when making use of a new path. The experimental results show that the use of multiple paths can reduce the impact caused by retransmissions in 25 % and 20 % of the average packet latency for 22 and 65 nm CMOS technologies, respectively. Moreover, the proposed technique can contribute to greater adaptability to faults on links and could be better investigated in future work under circumstances of heavy traffic and for 3D NoCs.