Pré-processamento de cenários para reconfiguração de roteamento eficiente em MPSOC baseado em NoC tolerante a falhas

Abstract

The latest technologies of integrated circuit manufacturing allow billions of transistors to be arranged on a single chip, enabling us to implement a complex parallel system, which requires a communications architecture with high scalability and high degree of parallelism, such as a Network-on-Chip (NoC). These technologies are very close to physical limitations, which increases the quantity of faults in circuit manufacturing and at runtime. Therefore, it is essential to provide a method for fault recovery that would enable the NoC to operate in the presence of faults and still ensure deadlock-free routing. The preprocessing of the most probable fault scenarios allows us to anticipate the calculation of deadlock-free routing, reducing the time that is necessary to interrupt the system during a fault occurrence. This work proposes a technique that employs the preprocessing of fault scenarios based on forecasting fault tendencies, which is performed with a fault threshold circuit operating in agreement with high-level software. The technique encompasses methods for dissimilarity analysis of scenarios based on cross-correlation measurements of fault link matrices, which allow us to define a reduced and efficient set of fault coverage scenarios. Experimental results employing RTL simulation with synthetic traffic prove the quality of the analytic metrics that are used to select the preprocessed scenarios. Furthermore, the experiments show the efficacy and efficiency of the proposed dissimilarity methods, quantifying the latency penalization when using the coverage scenarios approach