Análise de falhas de coprocessadores compartilhados em um MPSoC para estender o ISA RISC-V

Abstract

Reduced Instruction Set (RISC) architectures optimize a complex ISA by implementing only the most frequently used instructions in hardware. However, the application execution time significantly increases when executing heavily used instructions in software. One technique that optimizes the trade-off of implementation cost and execution time is the use of a Multiprocessor System-on-Chip (MPSoC), in which processors extend their ISA by sharing coprocessors that implement lesser-used instructions. In this work the impact of shared coprocessor failures on two RISC-V MPSoC architectures is analyzed. In the first phase, we evaluated these architectures using two image processing applications and four different models of failure rates in terms of power dissipation, energy consumption, area consumption, maximum operating frequency, and execution time. The experiments in this phase show a maximum increase of 16% in execution time for the application with a lower percentage of instructions executed on the coprocessor. For the application with the highest rate of coprocessor use, the execution time does not increase significantly in the proposed architectural configurations for the MPSoC after the first failure scenario. For the second phase of the work, the MPSoC was expanded to allow testing with six different models and four failure rates. The experiments in this phase showed a 34% increase in execution time for the application with a lower rate of instructions executed on the coprocessor. For the other application, the increase reached 92% in execution time.