Técnicas de modulação aplicada às estruturas de multiníveis com neutro grampeado e capacitor flutuante para redução de perdas e distorção harmônica

Abstract

In order to overcome the challenge of processing electric energy in high power systems with minimal losses and high energy quality, this work presents the implementation and analysis of a modulation technique applicable on both most well-known multilevel inverter structures - neutral point-clamped (NPC), and flying capacitors (FC) - to reduce the stresses across the semiconductors devices, and to improve the total harmonic distortion of the output voltage. Throughout the work, the necessity to digitalize the proposed technique has been evidenced due to the high complexity and low reliability inherent to the analogical approach. Thus, the digital controller FPGA has been chosen, as it is easy to program and reconfigure, works at high speed, and has a lot of input and output pins. Additionally, other modulation techniques were also implemented to compare their performance with the proposed one, presenting the switching patterns and the behavior of the electrical currents through the semiconductors for each modulation. A theoretical analysis was also performed for both topologies and their respective operation principle, characteristics, and equations used on the losses analysis for the different combinations of modulation applied to each structure. Finally, the digital development of the various techniques has proved to be correct by observing the waveforms obtained through the digital/analogical circuit. Besides, the comparison of the modulation techniques on 6 kW NPC and FC three-level prototype inverters proved to be favorable to the proposed technique in terms of efficiency and total harmonic distortion reduction on both topologies, confirming its usefulness on high power multilevel converters. At last, it was presented the application of the proposed modulation technique to inverters with more than three levels, where it was observed its eligibility for n-levels topologies.